Modern electronic products, including, for example, consumer electronics, computers, telecommunication equipment and automobile electronics use flip-flop circuits to store data during data processing operations. Flip-flop circuits are bistable circuits having output signals assuming one of two stable states based on a signal level or signal transition of an input signal.
D-Flip-Flop, also known as data-Flip-Flop is a fundamental circuit block in digital logic circuits and is quite frequently used block in transmitters and receivers. However, transmitters and receivers are still electrical in nature and do not work at very high speed, for example emerging optical links target more than 100 Gb/s capacities. This speed limitation is primarily from the circuits of the receiver and transmitter involved in communication links. Accordingly, the channel bandwidth is underutilized. However, if transmitters and receivers can work at high speed then the available channel may be utilized efficiently. To achieve a high speed of more than 100 Gb/s, Bi-CMOS technologies can be used; however due to their high cost they are usually not taken into account. CMOS technologies are good replacement of Bi-CMOS technologies but are slow in nature.
D-Flip-Flops with master-slave configuration are generally used in high speed applications. The present master-slave flip-flop comprises a master latch and a slave latch having respective data inputs, data outputs, and clock inputs, with the data output of the master latch connected to the data input of the slave latch. The data input of the master latch is the flip-flop's data input, and the data output of the slave latch is the flip-flop's data output.
In high speed application the devices are generally made wide to carry large amount of current which increases the input capacitance. D-Flip-Flops are also driven by source which has finite output impedance. These factors such as parasitic resistances and capacitances lead to input data having inter-symbol interference in D-Flip-Flops. It causes erroneous output and jitter.
Furthermore, inverter delays and switching delays in relation to the clock signal transitions, referred to as setup and hold delays, limit the speed at which a latch is able to setup and hold data represented in the input signal. Conventional latches have setup and hold delays of typically several picoseconds. In other words, there is an interval of several picoseconds before a clock signal transitions from a sample period to a hold period, wherein no change in the output signal would likely occur despite a change in the input signal. As a result, conventional latches are undesirably limited to processing signals having higher data rates.
In communication links such as serializers/deserializers, clock to data recovery (CDR) circuits, frequency dividers, delay elements etc., inductive peaking, active feedback technique, capacitive degeneration, T-coil techniques etc. are generally used to increase speed of high speed modules. However such modifications are neither cost effective nor do they provide a required result in an efficient manner.
Nevertheless, a need exists in the electronic industry to process data at even greater data rates.